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Welcome to the ITTC Wiki.

This site hosts web based collaboration areas for many research projects at the Information Technology and Telecommunications Center (ITTC) at the University of Kansas.


ITTC Research Labs

The Computer Systems Design Laboratory (CSDL)

The Computer Systems Design Laboratory (CSDL) will improve the design of computing systems, ranging from small, embedded elements to large, distributed computing environments. Research addresses all aspects of a system’s life cycle, including specification and synthesis. This includes attention to system verification, design, and implementation of development and implementation platforms for real-time and embedded computing.

The CSDL maintains some documentation on Software Tools that are used in the lab and also, as part of our lab research activites, we maintain a Reading Group where we read papers from the literature.

ITTC Research Projects

GpENI: Great Plains Environment for Network Innovation

The Great Plains Environment for Network InnovationGpENI (pronounced [dʒɛˈpi ni] with accent on the middle syllable and rhyming with GENI) is a regional network between The University of Kansas (KU), Kansas State University (KSU), University of Nebraska – Lincoln (UNL), and University of Missouri – Kansas City within the Great Plains Network, supported with optical switches from Ciena interconnected by Qwest fiber infrastructure, in collaboration with the Kansas Research and Education Network (KanREN) and Missouri Research and Education Network. GpENI is undergoing significant expansion to Europe and Asia using various tunneling protocols. GpENI is funded in part by the National Science Foundation GENI (Global Environment for Network Innovations) Program, as well as by the participating institutions that are contributing substantial resources.

The HybridThreads Project

The Hybridthreads systems is a real-time operating system (RTOS) which is built around a hardware/software codesign methodology. The system is designed as a new way to facilitate cooperation between hardware based computations and software based computations. The foundational idea behind the Hybridthreads system is that communication between hardware and software components should be no more difficult than communication between software components.

To implement this kind of transparent communication the Hybridthread system abstracts both hardware components and software components into threads which implement black box compuations. Communication between threads is accomplished through the use of shared memory and synchronization objects. These abstractions are well known and well understood as evidences by the vast number of complex systems which have been designed using them.

The HybridThreads project has recently moved to the University of Arkansas at The KU-based HybridThread page can still be found at KU Hybridthreads Project.

Postmodern Internetwork Architecture (PoMo)

We propose to design, implement, and evaluate through daily use a minimalist internetwork layer and auxiliary functionality that anticipates tussles and allows them to be played out in policy space, as opposed to in the packet- forwarding path. We term this design a postmodern internetwork architecture because it is a reaction against many established network layer design concepts. The overarching goal of the project, and the motivation for choosing a minimal networking layer, is to make a larger portion of the network design space accessible without sacraficing the economy of scale offered by agreeing on a common set of protocols. The primary tenets of our postmodern design are (i) strict separation of concerns, and (ii) inclusion of explicit mechanisms in support of all foreseeable policies influencing network-layer behavior.

The ResiliNets Initiative: Resilient and Survivable Networking

Society increasingly relies on computer networks in general, and the Internet in particular. Consumers rely on networks for access to information and services, personal finance, and for communication with others. The Internet has become indispensable to the routine operation of businesses and to the global economy. The military depends on network centric operations and warfare. Governments depend on networks for their daily operation, service delivery, and response to natural disaster and terrorist attacks.

Therefore, the consequences to disruption of the network are increasingly severe, and threaten the lives of individuals, the financial health of business, and the economic stability and security of nations and the world. With the increasing importance of the Internet, so follows it's attractiveness as a target from bad guys: recreational and professional hackers, terrorists, and from information warfare.

We therefore regard resilience and survivability as critical to the future of our network infrastructure. The ResiliNets initiative aims to understand and progress the state of resilience and survivability in computer networks, including the Global Internet, PSTN, SCADA networks, mobile ad-hoc networks, and sensor networks.

The Run-Time Reconfiguration Group

Advantages in Information Technology continue to play a vital role in our nation's ability to innovate and compete in the global market. Advancements in computing performance -- especially in the embedded computing systems domain -- are enabling these advantages. This project combines commercially available, hybrid devices (that is, single integrated circuits with processors, memory, and configurable hardware) and a novel run-time system with the goal of building systems with better performance and fewer resources. To accomplish this, the project is investigating and developing technology in two steps. First, every subroutine in the embedded systems application is processed to find those suitable for acceleration by configurable hardware and a new hardware feature is synthesized. Then, as the application executes, the run-time system continually reconfigures the hardware to keep the most profitable features resident. By carefully managing the overhead introduced, the aim of this work is to provide the performance advantages of custom hardware with fewer physical resources. The advantage of the particular system under investigation is that it automates reconfiguration -- which presently is an engineering-intensive, manual process. To test the effectiveness of this approach, the University of Kansas has teamed with Grand Valley State University to judge the performance of the system on applications developed by senior undergraduate students.

System-Level Design Group

The System-Level Design Group (SLDG) is a collection of faculty and students examining the application of formal, language-level techniques to system-level design issues. Research projects include the Rosetta for specifying system-level requirements; the InterpreterLib project for rapid deployment of interpreters and comonadic simulators; and numerous applications of system-level design techniques. Our work is done in the non-strict, lazy functional language Haskell. In particularly we make heavy use of monadic and comonadic constructs. The SLDG is the primary sponsor of the Lambda language semantics reading group.

The SLDG wiki is maintained primarily for discussion of dynamic projects within the group. Our website contains more stable information about the group and our research.

The CogNet Project

The CogNet initiative at the University of Kansas is performing research on architectural tradeoffs and protocol design approaches for cognitive networks at both local network and the global internetwork levels. The initiative is investigating architectural issues including naming, addressing, and routing, collaborative control & management protocols, and experimental system evaluation using measurement & management overlays and cognitive wireless implementations.

ITTC Reading Groups

The Lambda Group

The Lambda Group is an informal reading group organized by SLDG students to discuss topics related to programming and specification languages, semantic models, and programming paradigms. As the name implies, the group tends towards functional languages such as Haskell, Scheme and ML.

RC Reading Group

The Runtime Reconfiguration Reading Group is organized by CSDL students to discuss topics related to FPGAs and, specifically, runtime reconfiguration of FPGAs. The group is open to anyone who wishes to attend.

EECS Classes

EECS 140 - Introduction to Digital Logic Design

An undergraduate introductory course in digital logic circuits covering number representation, digital codes, Boolean Algebra, combinatorial logic design, sequential logic design, and programmable logic devices. EECS 140 Lab Page

EECS 168 - Programming I

Problem solving using a high level programming language and object oriented software design. Fundamental stages of software development are discussed: problem specification, program design, implementation, testing, and documentation. Introduction to programming using object oriented language: using classes, defining classes, and extending classes. Introduction to algorithms and data structures useful for problem solving: arrays, lists, files, searching, and sorting. Student will be responsible for designing, implementing, testing and documenting independent programming projects. Professional ethics are defined and discussed in particular with respect to computer rights and responsibilities

EECS 268 - Programming II

This course continues developing problem solving techniques by focusing on the imperative and object-oriented styles using Abstract Data Types. Basic data structures such as stacks, queues, and trees will be covered. Recursion. Basic notions of algorithmic efficiency and performance analysis in the context of sorting algorithms. Basic Object-Oriented techniques. An associated laboratory will develop projects reinforcing the lecture material. Three class periods and one laboratory period per week.

EECS 388 - Computer Systems & Assembly Language

An undergraduate-level class that covers basic computer architecture by introducing basic computer system structure: CPU, busses, ISA, memory-mapped components, etc. This class is FPGA-based and will use the XUP-V2P development boards and MicroBlaze soft-core processors to develop embedded systems-on-chip.

EECS 560 - Data Structures

An introduction to data structures.

EECS 665 - Compiler Construction

An introduction to compilers. Next offering will be Fall 2007.

EECS 700 - Reconfigurable Computing

A graduate level course discussing reconfigurable computing technology. This class is organized as a discussion of recent and on going research in the area of reconfigurable technology. As such, studnents in the class are expected to be capable of reading and analysing published research.

EECS 740 - Image Processing

The Image Processing pages describe basic image processing concepts from EECS 740 and ongoing research in this area at KU.

EECS 753 - Embedded and Real Time Systems

A graduate level course on advanced topics in embedded and real time systems. This course will cover the fundamental principles, and new technologies and methods in use for specifying and designing embedded and real time systems.

EECS 755 - System Requirements Modeling

An advanced introduction to system modeling and formal methods. Next offering will be Fall 2007.

EECS 780 - Communication Networks

Comprehensive in-depth coverage of communication networks with emphasis on the Internet and the PSTN (wired and wireless). Extensive examples of protocols and algorithms are presented at all levels, including: client/server and peer-to-peer applications; session control; transport protocols, the end-to-end arguments and end-to-end congestion control; network architecture, forwarding, routing, signalling, addressing, and traffic management; quality of service, basic queuing (basic M/M/1 and Little's law) and multimedia applications; LAN architecture, link protocols, access networks and MAC algorithms; physical media characteristics and coding; network security and information assurance; network management.

EECS 881 - High-Performance Networking

Comprehensive coverage of the discipline of high-bandwidth low-latency networks and communication, including high bandwidth-×-delay products, with and emphasis on principles, architecture, protocols, and system design. Topics include high-performance network architecture, control, and signalling; high-speed wired, optical, and wireless links; fast packet, IP, and optical switching; IP lookup, classification, and scheduling; network processors, end system design and protocol optimization, network interfaces; storage networks; end-to-end protocols, mechanisms, and optimizations; and high-bandwidth low-latency applications. Principles will be illustrated with many leading-edge and emerging protocols and architectures.

Advanced Computer Architecture - Multiprocessor Systems On Chip

A graduate level course on advanced topics in computer architecture. The focus of this course will be Multiprocessor Systems on (Programmable) Chips (MPSopC).

Motorola HC12 - EECS 388 - Computer Systems & Assembly Language

An undergraduate-level class that covers elementary computer architecture by introducing basic computer system structure: CPU, busses, ISA, memory-mapped components, etc. This class is based upon the age-old Motorola HC12 in the form of the Axiom development board.